This report provides instructions for installing and using the VHDL Synthesis System (Version 5.0). VSS is a high level synthesis sytem that synthesizes structures from an abstract description, written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS). The output of VSS is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. VSS is also capable of producing different architectures which can be selected by the designer.
