UC Santa Barbara

This work presents the efforts pursued to improve InGaAs/InP FET technologies for high frequency applications. Self-Aligned MOS-HEMTs were developed using a sacrificial InP layer and a diluted HCl sacrificial etch. The new process removes the previous issue of misalignment in MOS-HEMT technology. In addition, the self-aligned process results in a new “V-gate” as opposed to the tradition “T-gate”. This new gate technology no longer requires the bi-layer resist used in traditional HEMT technology and allowed for gate footprint scaling from 50 nm to 20 nm. To improve processability and high frequency performance, a theory on the effects of topside link thickness on resistance, capacitance, and cut off frequency was proposed. Traditionally, HEMTs have thick link regions to keep the donor ions far from the mobile charge in the channel. This keeps scattering and resistance in the source low; however, this places more material in between the source and the gate and increases capacitance. Simply, the theory states that as transistors continue to scale, the mobility of the link becomes less dominant than the extrinsic source gate capacitance when considering optimal link thickness. In the new process, CGS + CGD was reduced by a total of 40% compared to previous MOS-HEMTs. With these improvements, a Lg = 20 nm device, exhibiting fτ = 525 GHz, fmax = 709 GHz, and a Lg = 36 nm device, exhibiting fτ = 479 GHz, fmax > 1 THz were demonstrated.