UC Irvine

One of the fundamental challenges to the performance gain in advanced semiconductor technology

is aging-induced delay degradation of transistors, which consequently increases the

logic gates delays and eventually critical paths delays. Hence, designers have to add significant

time margin as guardband to the main critical path, which imposes considerable

performance degradation to the system. Temperature and stress (or usage) are the major

sources of transistor’s aging, which vary for different applications and are highly workload

dependent. This thesis covers challenges and opportunities in monitoring aging, its effects

and methods to combat the imposed performance and lifetime degradation in nanometer

scales semiconductor platforms.

We devise methods to monitor and mitigate aging in computing platforms ranging from

the conventional reconfigurable architectures to the contemporary 3D network-on-chips and

many-core systems. To monitor aging-induced delay degradation on critical paths, we proposed

SENSIBLE, a highly scalable aging sensor design that can help system-level designers

to detect aging and react accordingly. Additionally, we proposed an application-dependant

filtering methodology to select Representative Critical Paths (RCPs) among a large pool of

critical paths for aging monitoring in reconfigurable architectures. Furthermore, two proactive

methods are presented to mitigate aging impacts on application’s critical paths and SRAM cells in reconfigurable architectures. The former is a high-level physical planning

coupled with a reconfiguration policy and the latter is STABLE, a post-synthesis stress aware

Boolean matching technique. To mitigate and monitor aging on Network on Chip

(NoC) components in both 2D and 3D IC designs we proposed AROMa, which is an aging-aware

adaptive routing algorithm. To this end, we devised Centralized Aging Table (CAT) to

convert transistor level aging phenomenon to the workloads’ behavior in NoC-based manycore

systems. Finally, an aging-aware task mapping, ADAMANT, is proposed to balance

aging in many-core heterogeneous architectures’ components.