UCLA

With the coming era of Big Data, hardware implementation of machine learning has become attractive for many applications, such as real-time object recognition and face recognition. Performance of this kind of applications is determined by the robustness of memory access and monitoring of the circuit uncertainty. As current nanotechnology semiconductor device scaling down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also circuit layout and interconnect. Hence to accurately measure and model interconnect parasitic in order to predict interconnect performance on silicon, a set of test structures that can be used to study the timing performance (i.e. propagation delay and crosstalk) of various interconnect configurations was developed. To improve the validation of the higher order layout effects (WPE, OSE and PSE), Design for Manufacturability (DFM) impacts of two analog layout structures, guard ring and dummy fills impact were monitored with current mirror test circuit using TSMC 28nm HPM process. Finally, a new design of high-speed SRAM with fast access time (cycle time: 650 ps, access time: 350 ps), low sensitivity to temperature variation and high reconfigurability (less than 10% performance difference between 125_rcw_tt vs 0_rcw_tt) was developed. These results described in this thesis provide comprehensive solutions to the requirement of the circuit uncertainty monitoring and rapid memory access of machine learning hardware implementations.