UC Irvine

Technology scaling and higher operational frequencies are no longer sustainable at the same pace as before. The processor industry is rapidly moving from a single core with high-frequency designs to many-core with lower frequency chips; Network-on-Chip (NoC) has been proposed as a scalable and efficient on-chip interconnection among cores. In addition, employing Three-Dimensional (3D) integration instead of Two-Dimensional (2D) integration is the other trend to keep the traditional expected performance improvements. The combination of 3D integration and NoC technologies provides a new horizon for on-chip interconnect design. In more detail, the reduction of the length and number of global interconnects; by applying Through-Silicon Via (TSV) is the major advantage of 3D NoCs.

However, shrinking transistor sizes, smaller interconnect features, and 3D packaging issues, lead to higher error rates and unexpected timing variations. Although many researches have focused on reliability issues for 3D NoC architectures, To develop a general technique to advance both the intuitive understanding and the quantitative measurement of how potential physical faults influence the behavior of 3D NoC is lacking. The goal of my dissertation is to develop a Three-Dimensional NoC Reliability ity Evaluation Automated Tool (TREAT), for the first time, as an automated analysis tool to analyze effects of static and dynamic faults in 3D NoC architectures. It is capable of evaluating the vulnerability of different architectural components in the presence of faults by using the fault injection method. This approach allows injecting faults into the 3D NoC platform dynamically by monitoring the status of links and components to decide where and when inject faults accurately. TREAT provides the strength of different components in terms of reliability-based metrics such as Mean Time Between Failure (MTBF) and header/data/trailer flit failure rate for different level of granularity. The output reports of TREAT are critical in devising fault-tolerant techniques with low overhead cost. TREAT can be used at the early stage of the design process in order to prevent costly redesigns after assessing dependability for the target architecture.

Comparing to existing fault injector tools, TREAT is specifically developed for 3D NoC platforms and it is not a general fault injector tool. Such a tool is needed since the characteristics and behavior of a 3D NoC component is different from other computational platforms; 3D NoCs are susceptible to different fault sources that are not

fully addressed by existing tools. Furthermore, one of the most important advantages of TREAT is supporting dynamic fault injection by monitoring the status of the NoC platform. This is critical since based on the reported experiments in this dissertation, random TSV coupling fault injection may result in 26%-99% inaccuracy of reliability evaluation process. The fault injector interface is responsible for injecting fault accurately where and when they should in order to enhance the reliability evaluation. None of the existing tools offer these capabilities as a single package.