UCLA

To support the increasing demand of various high data-rate wireless communications, the 7 GHz band at 57-64 GHz has been allocated by the FCC for unlicensed system applications. This decision results in the formations of several standards aiming to develop multi-gigabit wireless communication systems, e.g., IEEE 802.15.3c, IEEE 802.11ad, and WiGig, among many others. One of their common and ultimate goals is to expedite the realization of widespread integrated circuits supporting large data transfers over the air.

Designing a digital baseband receiver for the 60 GHz communication system (802.15.3c/802.11ad) requires the following features: (1) a proper architecture to mitigate design challenges of the high-speed analog-to-digital converters (ADCs) that are required by the synchronizer of the receiver; and (2) an effective technique to decouple the interferences that result from adjacent channel estimation sequences (CESs) as well as degrade the equalizer performance of the receiver.

To fulfill these requirements, this work realizes the following: (1) a fractional-sampling-rate (FSR) digital baseband receiver to relax the ADC sampling rate requirement through multi-rate signal processing techniques; and (2) a high-accuracy channel estimator to reconstruct interference-less CES responses for improving the BER performance of the equalizer. Compared with the prior arts, the 65 nm CMOS implementations of (1) and (2) demonstrate the feasibilities of reducing the required ADC sampling rate by 25%, and assisting the equalizer in achieving 170x BER reduction, respectively.