UCLA

With wireless communications becoming an essential part of human life, wireless technology advances to meet the increasing demands. New standards are introduced every couple of years to regulate the implementation of wireless systems. Most of modern standards are based on MIMO and OFDM signaling, which makes any time saving in a MIMO-OFDM receiver design cycle essential and the support of multi-standards in the same device highly desirable.

This work introduces a hardware implementation for a MIMO decoder accelerator, which is a software-programmable device that specializes in MIMO decoding, and MIMO signal processing in general, for OFDM systems. A VLSI implementation of the accelerator is introduced highlighting some of the implementation decisions and techniques to minimize the overall energy consumption of the accelerator hardware. The accelerator chip core area is 2.48mm2 in 65nm CMOS technology. Its average power consumption is 224.3 at 166MHz clock frequency. A deeply pipelined design for a powerful processing core allows the accelerator to achieve energy consumption figures competing with specialized designs. A single accelerator chip can be programmed to complete 4x4 QR decomposition, 4x4 Singular-Value Decomposition (SVD), 2x2 MMSE MIMO decoding, 4x4 MMSE MIMO decoding, or many other possible applications.

A simple design flow is presented to assist a MIMO-accelerator user in mapping a MIMO-related algorithm to a successful accelerator-based hardware implementation in no time. The accelerator, with its diversity and energy efficiency, can empower a wireless MIMO-OFDM receiver giving it an unparalleled advantage over regular fixed-data-path systems.