UCLA

The growing demand for high-speed communication has led to a twofold increase in the per-lane data rate every four years across various wireline standards. As a result, the power consumption of high data rate transceivers has become critical. Moreover, the bandwidth of different blocks within a transceiver must accommodate the operating speed so as to avoid eye closure. These concerns call for either implementation in expensive sub-10nm FinFET technologies, or new circuit- and system-level novelties realized in less-advanced CMOS nodes.This work introduces a PAM4 transmitter (TX) that incorporates a number of new techniques to achieve a low power consumption, while delivering data at 112 Gb/s. A resistorless voltage-mode output DAC relies merely on the on-resistance of the transistors within LSB and MSB inverters for proper termination, thereby relaxing the capacitive loading of the data and clock paths, hence lower power. The PAM4 nonlinearity due to nonlinear resistances is alleviated by scaling up the LSB section, as well as employing separate LDOs for LSB and MSB for fine calibration. Furthermore, a 3-tap latchless FFE provides a high-frequency boost with minimal power. Lastly, a new skew compensation network adjusts the skew experienced by the differential signal in an asymmetric channel. The TX includes a latchless serializer and an on-chip PLL. Fabricated in 28-nm CMOS technology, the transmitter draws 58 mW and exhibits a swing of 0.8 Vpp,d, rms clock jitter of 160 fs and RLM = 96%.