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Analytical methods for VLSI module placement

Abstract

Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just few to mention in the list of complexities. With these complexities in mind, placers are faced with the burden of finding a spatial arrangement of components under strict wirelength, timing, and power constraints. Motivated by this challenge, this thesis presents our work on a general analytical placement framework and its applications to a variety of placement tasks. The first part of this thesis describes the basic architecture and technical details of our high-quality, large-scale analytical placer, APlace. We describe (i) a constrained minimization formulation for the global placement problem, (ii) a top-down multi-level global placement algorithm, and (iii) legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark suites. The analytical placement framework has strong extensibility, and we have applied variants of APlace to several novel placement tasks. The second part of this thesis describes the following applications: (1) a timing-driven placement method with net weighting for performance improvement, (2) a power-aware placement method with clock register clustering and activity-based net weighting for clock power and switching power reduction, (3) a voltage degradation (IR drop) aware placement method that relocates cells for supply voltage drop improvement, (4) a lens aberration aware timing-driven placement method with awareness of across-field lens aberration effects for timing yield optimization, and (5) other applications to I /O-core co-placement and constraint handling for mixed- signal contexts. The results obtained suggest that the APlace framework can offer practical value in a wide variety of contexts

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