UC Berkeley

The development of nanoscale MOSFETs has given rise to increased attention paid to the role of parasitic source/drain and contact resistance as a performance-limiting factor. Dopant-segregated Schottky (DSS) source/drain MOSFETs have become popular in recent years to address this series resistance issue, since DSS source/drain regions comprise primarily of metal or metal silicide. The small source/drain extension (SDE) regions extending from the metallic contact regions are an important design parameter in DSS MOSFETs, since their size and concentration affect contact resistance, series resistance, band-to-band tunneling (BTBT), SDE tunneling, and direct source-to-drain tunneling (DSDT) leakage. This work investigates key design issues surrounding DSS MOSFETs from both a modeling and experimental perspective, including the effect of SDE design on ambipolar leakage, the effect of random dopant fluctuation (RDF) on specific contact resistivity, 3D FinFET source/drain and contact design optimization, and experimental methods to achieve tuning of the SDE region.

It is found that DSS MOSFETs are appropriate for thin body high performance (HP) and low operating power (LOP) MOSFETs, but not low standby power (LSTP) MOSFETs, due to a trade-off between ambipolar leakage and contact resistance. It is also found that DSDT will not limit DSS MOSFET scalability, nor will RDF limit contact resistance scaling, at the end of the CMOS roadmap. Furthermore, it is found that SDE tunability in DSS MOSFETs is achievable in the real-world, for an implant-to-silicide (ITS) process, by employing fluorine implant prior to metal deposition and silicidation. This is found to open up the DSS process design space for the trade-off between SDE junction depth and contact resistance. Si(1-x)Ge(x) process technology is also explored, and Ge melt processing is found to be a promising low-cost alternative to epitaxial Si(1-x)Ge(x) growth for forming crystalline Si(1-x)Ge(x) films.

Finally, a new device structure is proposed, wherein a bulk Tri-Gate MOSFET utilizes high-k trench isolation (HTI) to achieve enhanced control over short channel effects. This structure (the HTI MOSFET) is shown, through 3D TCAD modeling, to extend bulk LSTP scalability to the end of the CMOS roadmap. In a direct performance comparison to FinFETs, the HTI MOSFET achieves competitive circuit delay.