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Open Access Publications from the University of California

A 53-61GHz Low-Power PLL in 65nm CMOS

  • Author(s): Abedi, Razieh
  • Advisor(s): Heydari, Payam
  • et al.
Creative Commons 'BY-ND' version 4.0 license

A 53-61GHz low-power charge-pump PLL is presented. This integer-N type-II PLL employs a class-D V-band VCO, a divide-by-1024 chain. The first divider in the chain is an inductor-less divide-by-4 injection-locked frequency divider (ILFD). The proposed PLL is fabricated in a standard 65nm CMOS process. The PLL achieves a tuning range of 13% from 53.35GHz to 60.83GHz and a phase-noise of -85.23dBc/Hz at 1MHz offset, while consuming a minimum DC power of 50.8mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers.

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