Donald Bren School of Information and Computer Sciences

In this report we describe the design process for behavioral synthesis from VHDL descriptions. The design process can be divided into two parts, (a) the architectural allocator (AA), which derives the appropriate type and number of resources (storage, functional units, and buses) that can satisfy the area and performance constraints imposed by the designer, and (b) the VHDL SynthesisSystem (VSS), which synthesizes a RT-level netlist based on the allocation constraints. The human interface for all the tasks in the design process is also described in this report.