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100Gbps Half-Rate Referenceless Injection-Locking Clock/Data Recovery Circuit in 0.18 µm BiCMOS Process

  • Author(s): Samavaty, Behzad
  • Advisor(s): Green, Michael
  • et al.
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Abstract

The demand for bandwidth intensive applications has increased significantly in the last decade. Applications such as video streaming, cloud-based computing, cloud storage and Internet of Thing (IoT) have created a demand that has rushed deployment of high-speed transceivers of 100 Gb/s and even 400Gb/s. The design of a clock/data recovery circuit is one of the most challenging blocks in a broadband receiver. One of those challenges is the frequency acquisition range, which is naturally quite low for the phase detectors used in such circuits, thereby necessitating additional circuitry to enhance this acquisition range. Another challenge is the slow locking time exhibited by conventional methods, which is undesirable for some applications. We propose a different approach, based on injection locking, that does not require an external reference clock, and thus can reduce the form factor of the overall transceiver. The chip is implemented in the standard 180nm BiCMOS process and represents the first implementation of a half-rate 100Gbps injection locking CDR. The CDR circuit occupies 0.36mm2 silicon area and the power efficiency is 2.9mW/Gb/s at 100Gb/s.

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This item is under embargo until April 5, 2020.