Donald Bren School of Information and Computer Sciences

An important task in the system level synthesis process is estimating design parameters such as area and performance that will characterize any implementation of the design. Estimates enable the designer to rapidly explore large search spaces and provide him/her with valuable feedback on the effect and feasibility of implementing certain design decisions. In this report, we present techniques for estimating the area and performance of a design specified using the SpecChart language which is a combination of hierarchical/concurrent state diagrams and VHDL.