UCLA

Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This dissertation addresses the “last inductor” problem and proposes both integer-N and fractional-N synthesizer architectures that achieve a phase noise and figure of merit (FOM) comparable to those of LC-VCO-based realizations.

A new wideband integer-N synthesizer is introduced to sufficiently suppress the ring’s phase noise. It employs an exclusive-OR (XOR) phase detector and a master-slave sampling filter (MSSF) to achieve a lock range of 2-3 GHz, a loop bandwidth equal to one half of the reference frequency, and a locked phase noise of -114 dBc/Hz up to 10-MHz offset with a 3-stage ring oscillator. Realized in 45-nm CMOS technology, the design uses a harmonic trap to suppress reference sidebands to less than -65 dBc while consuming 4 mW.

The wideband architecture has been successfully extended to a fractional-N loop as well. A ring-oscillator-based cascaded synthesizer incorporates a digital synchronous delay line and an analog noise trap to suppress the quantization noise of the Sigma-Delta modulator. Realized in 45-nm CMOS technology, the synthesizer exhibits an in-band phase noise of -109 dBc/Hz and an integrated rms jitter of 1.68 ps at 2.4 GHz with a power consumption of 6.4 mW.