UCLA

The rapid rise in demand for high data rates has led to communication standards like LTE that use signals with wide signal bandwidth and high peak-to-average power ratio. Since, total power consumption is largely determined by the efficiency of the power amplifier used, high efficiency architectures like polar and out-phasing, are preferable for future transmitter designs. Such architectures require a phase modulator (PM) as one of their key building blocks. The recent developments in phase modulator design have demonstrated superior wide-bandwidth performance of open loop modulation techniques. However, currently the resolution is limited by systematic errors inherent in the phase modulator circuit and random errors due to inevitable component mismatches.

In this dissertation, a phase-interpolator based open-loop phase modulator is proposed, which leverages a digital calibration technique to mitigate the sources of phase errors and achieves excellent phase resolution. At the heart of this technique, a time-to-digital converter performs high resolution measurement of phase errors of the phase modulator. These measurements are used to continuously pre-distort the modulation data, so that the linearity of the overall transfer function is enhanced, thereby resulting in low out-of-band emission and low in-band noise. A prototype IC was implemented in 0.13 m CMOS process. Measurements on the prototype show that out-of-band quantization noise is 56-dB lower than the signal when transmitting 20-Mb/s GFSK signal and the r.m.s. error is only 3.2%. The power consumption of the phase modulator is 18 mW. Since the IC was implemented in 0.13 m CMOS process, the power is expected to reduce a lot, if it is implemented in finer process nodes. The dissertation also presents theory and measurement results on frequency synthesis using the open-loop phase modulator. New frequency can be synthesized with very fine frequency step size, by applying a digital phase ramp to the phase modulator. However, the non-linearity of the phase modulator results in strong spurious tones. Digital compensation is proposed to mitigate these spurs, and generate multiple low-jitter clocks.