Department of Computer Science & Engineering

In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. Bounding load capacitance also improves reliability with respect to hot-carrier oxide breakdown and AC self-heating in interconnects, and guarantees bounded input rise/fall times at buffers and sinks. This report introduces a new minimum-buffer routing problem (MBRP) formulation which requires that the capacitive load of each buffer, and of the source driver, be upper-bounded by a given constant. Our contributions include the following. (a) We give linear-time algorithms for optimal buffering of a given routing tree with a single (inverting or non-inverting) buffer type. (b) For simultaneous routing and buffering with a single non-inverting buffer type, we give a factor $2(1+\varepsilon)$ approximation algorithm and prove that no algorithm can guarantee a factor smaller than 2 unless P=NP. For the case of a single inverting buffer type, we give a factor $4(1+\varepsilon)$ approximation algorithm. (c) We give local-improvement and clustering MBRP heuristics with improved practical performance and present a comprehensive experimental study comparing the runtime/quality tradeoffs of the proposed MBRP heuristics on test cases extracted from recent industrial designs.

Pre-2018 CSE ID: CS2001-0681