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Switched-capacitor silicon compiler

  • Author(s): Negahban-Hagh, Mehrdad
  • Gajski, Daniel
  • et al.
Abstract

A switched-capacitor (SC) silicon compiler will be described in this report. The input to this system is a set of specifications and a circuit description of an SC block. It has an opamp synthesis tool which is based on the selection and assembly of primitive modules. The opamp circuit topology is formed by searching through a set of styles yielding high performance opamp circuits serving a wide range of SC network applications. The layout strategy and architecture are such that they eliminate any crossover of sensitive signals by insensitive signals; Thus avoiding any special routing algorithm for sensitive routing. The results is a compact, parasitic-insensitive and "standard cell" type layout of an SC block with user-defined height. All blocks are placed and routed together by a general auto-placement and router tool.

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