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A New High-Speed ADC Architecture

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High-speed low-power analog-to-digital converters (ADCs) find application in communication systems and signal processing. The principal challenge in developing such ADCs stems from speed-power-resolution trade-offs. An attractive low-power solution is the successive approximation (SAR) architecture, but it suffers from a low conversion speed. This work introduces a SAR ADC that incorporates a number of novel techniques to push the speed without sacrificing power. A “look-ahead” architecture is presented that doubles the speed, as well as a new SAR logic circuit. In addition, a new method of clock generation and distribution for time-interleaved ADCs is demonstrated that lowers phase mismatches considerably. Realized in 28-nm CMOS technology, a 6-bit 10-GS/s prototype provides a signal-to-(noise+distortion) ratio of 31.2 dB at Nyquist, while drawing 17.6 mW. This results in a figure of merit of 59 fJ/cs, the lowest achieved to date.

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This item is under embargo until September 8, 2024.