A Placement Methodology for Global Interconnect Reduction and Its
Impact on Performance
Global interconnects are a bottleneck in today's high-performance deep-submicron designs. In this paper, we propose a modification to the top-down min-cut placement algorithm to reduce the number of global interconnects. Our method is generic and does not involve any timing analysis during or prior to placement. In essence, we skew the netlength distribution produced by a min-cut placer so as to reduce the number of long nets, with minimal impact on the overall wirelength. Empirically, this approach has negligible impact on placement runtime, but leads to a significant reduction in the number of global interconnects. The fewer interconnects translate to about 25% savings in the number of buffers required for signal integrity and electrical sanity, and also improve timing as measured by the worst negative slack and total negative slack of industrial benchmarks by up to 70% compared to a traditional min-cut placement flow (e.g., Capo 8.7).
Pre-2018 CSE ID: CS2004-0801