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Synthesis from VHDL : Rockwell-counter case study

  • Author(s): Gajski, Daniel
  • Lis, Joseph
  • Zanden, Nels Vander
  • Wu, Allen
  • et al.
Abstract

This report describes the design process and synthesis tools used in the UC Irvine CADLAB design environment to design a representative benchmark. The steps taken and rationale used in each stage of the design process are discussed. The benchmark is initially described using a VHDL behavioral description; results produced by each intermediate tool are presented, showing the system flow and integration of tools. The final silicon layout is performed in 3 micron CMOS technology.

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