UC Irvine

Over the past 30 years, research on CMOS radio-frequency (RF) front-end circuits has progressed extremely quickly. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. The design is simulated with cadence tool, the design kit is from IBM 130nm.

In this thesis, the basic 2.4 GHz heterodyne receiver was designed on a 130um CMOS process. In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The design reaches the NF of 2 dB, has power consumption of 2.2 mW, and has a gain of 20dB.

The second part of this thesis presents a low power 2.4GHz down conversion Gilbert Cell mixer. The obtained result shows a conversion gain of 14.6dB and power consumption of 8.2mW at a 1.3V supply voltage.

In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology. The final simulation of the phase noise is -128 dBc/Hz, and the tuning range is 2.3GHz- 2.5GHz while the total power consumption is 3.25mW. The performance of the receiver meets the specification requirements of the desired standard. In future work, a more compactly designed topology will be presented.