UCLA

Abstract—In this letter, charge trapping behavior in 22-nm technology high-k-metal-gate SOI CMOS logic devices is analyzed under various bias stress and self-heating conditions. It is observed that the charge trapping is not only dependent on the channel power density during stress, which is controlled by drainbias and device channel length, but is also strongly modulated by the device channel width. Thus, identical power densities in devices with different channel widths result in significantly different charge trapping behaviors. It is shown that device self-heating is strongly influenced by the device channel width and that the channel temperature during the charge injection process significantly impacts the magnitude and stability of the trapped charge. We discuss the implications of the findings for the application of high-k-metal-gate logic devices as embedded memory elements for non-volatile data storage in high-k-metal-gate CMOS technologies without added process complexity.