Skip to main content
USING 3D INTEGRATION TECHNOLOGY TO REALIZE MULTI-CONTEXT FPGAS
Published Web Location
http://www1.cs.ucr.edu/faculty/philip/papers/conferences/fpl09/fpl09-3dfpga.pdfNo data is associated with this publication.
Abstract
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). The latency between reconfigurations, 8.42μs, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts. ©2009 IEEE.
Many UC-authored scholarly publications are freely available on this site because of the UC's open access policies. Let us know how this access is important for you.