## Physical and Compact Modeling of vertical and lateral tunnel field effect transistors

- Author(s): Min, Jie
- Advisor(s): Asbeck, Peter M.
- Taur, Yuan
- et al.

## Abstract

With the scaling of MOSFET devices down to the sub-10 nm regime, there has been an active search for novel designs and device physics for lower $V_{DD}$ operation. For MOSFETs, the theoretical limit of 60mV/dec sub-threshold slope has posed a lower limit for $V_{th}$ below which leakage current in OFF-state is undesirably high for digital circuit applications and consequently a limit for supply voltage $V_{DD}$ . What's more, short channel effects such as drain induced barrier lowering (DIBL) has also been a challenge for every iteration of technology node below 100nm. Tunnel field effect transistor, a design that utilizes band-to-band tunneling (BTBT), becomes a promising candidate because of its capability in achieving sub-60mV/dec, more resistance to short channel effects and less temperature dependent characteristics, especially in OFF-state.

This thesis focuses on the modeling of tunnel FETs in a variety of aspects, including analytic modeling; temperature dependent factors and physical noise analysis of double gate tunnel FET structures; and compact modeling and physical analysis of vertical tunnel field effect transistors with a distributed circuit model.

In the analytic modeling of double gate TFET work, an analytic tunnel barrier model for TFET is formed by solving a 2D homogeneous Poisson equation. The approximate solution, an exponential function for long channel barrier and a $sinh$ function for short channel barrier, is proposed to replace the Kane's tunnel model, which assumes a constant field and homo-junction for tunneling. Tunneling probabilities are thus evaluated analytically for exponential barrier conditions, and current density is integrated numerically. Furthermore, short channel effect, source doping effect, debiasing effect (which details how the carriers accumulated in the channel affect the potential profile in the linear region), and dimensionality dependence (dimension of density of states) are further studied starting from the analytic expressions of tunnel barriers. The model shows much higher computational efficacy than the Sentaurus TCAD simulator and higher accuracy than a simple Kane model.

TFET is also desirable for the weak dependence of BTBT mechanism on temperature. Yet, there are other temperature dependent factors affecting the performance of TFET such as threshold voltage shift and effective tunnel gap shrinking. In this work, several possible temperature dependent factors that are intrinsic in semiconductors are studied for a double gate TFET, and their effects on $V_{th}$ and tunneling bandgap $E_g^{tun}$ are elaborated. These factors include bandgap shrinkage, temperature dependent Fermi-Dirac distribution in source region (source degeneracy) and temperature dependent effective DOS mass in the channel (which determines quantum confinement). It is found that there are canceling effects between quantum confinement, source degeneracy with bandgap shrinkage in $V_{th}$ calculation as well as tunnelling bandgap calculation. The canceling effects result in a weak dependence on temperature of both threshold voltage (affecting $I_{off}$) and tunnel bandgap (affecting $I_{on}$). One can further optimize the temperature dependence and ON-state current by tuning the device thickness. Trap-assisted tunneling (TAT), a temperature dependent extrinsic effect, is further simulated from a more practical standpoint. It is found that the TAT will mostly affect the current leakage floor rather than degrading the sub-threshold slope in a full current range.

Noise model is an essential for many circuit design simulations. To develop a noise model for a TFET involves different noise mechanisms and physics from the case for a MOSFET. In this work, frequency independent noise (white noise) and frequency dependent noise (flicker noise) are considered for a double gate TFET. For white noise calculation, both shot noise at the tunnel junction and thermal noise in the channel are considered for a device with 100nm gate length. Their individual contributions to drain terminal current are calculated using the impedance field method. As for flicker noise calculation, it is found from number and mobility fluctuation models aided by Sentaurus simulation that the most significant noise contribution originates near the tunnel junction in the saturation region of the $I-V$ curves, and mobility fluctuations become nontrivial in the linear region.

Finally, a novel structure where tunneling happens between two layers in a direction orthogonal to the source-to-drain net current flow direction ("vertical TFET") is studied using a distributed circuit model. Both vertical tunneling and lateral drift-diffusion model are considered in the overall calculation and the competitions between these two mechanisms are shown. A shorter gate length increases the conductivity in the lateral direction, but decreases the conductivity in the vertical direction. Therefore, there exists an optimized gate length for DC ON-current density. However, in terms of RF performance, it is found that shrinking the gate length boosts the cut-off frequency and the speed of transistors because of a major reduction in capacitance with little accompanying decrease of transconductance. Finally, parasitic elements are considered for more realistic RF modeling.