UC Santa Cruz

In a detector system where the number of channels exceeds the number of channels available on an application-specific integrated circuit (ASIC), there is a need to configure channels among multiple ASICs to achieve the lowest electronic noise and highest count rate. In this work, two board configurations were designed to experimentally assess which one provides the more favorable performance. In the half-half configuration, contiguous channels from one edge to the center of CZT detector are read by one ASIC, and the other half are read by the other ASIC. In the alternate configuration, the CZT channels are read by alternating ASICs. A lower electronic noise level, better FWHM energy resolution performance (5.35% ± 1.08% compared to 7.84% ± 0.98%), and higher count rate was found for the anode electrode strips with half-half configuration. Cross-talk between ASICs and deadtime play a role in the different performances, and the total count rate of the half-half configuration has a count rate 18.1% higher than that of the alternate configuration.