Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology
- Author(s): Wu, Chaoying (Charles);
- Advisor(s): Nikolic, Borivoje;
- et al.
Current advances in wireless receiver technologies are primarily driven by the need for cost reduction through (1) integration of a radio, an ADC and a digital processor on a single CMOS die, and (2) the design of low-power multi-standard capable receivers. However, due to the spectrum scarcity, future wireless standards, such as LTE, present a whole new set of challenges for radio system design. For example, LTE's highly fragmented spectrum requires multiple chipsets for support. Due to this cost overhead, there is no global LTE-enabled device available in the market now. Moreover, while carrier aggregation (CA) added to LTE brings unparalleled data rate improvement, it seriously complicates the RF frontend design. Modern commercial LTE solutions include multiple chipsets to support various scenarios of CA, which is not cost effective.
This work focuses on novel receiver architectures that address the design challenges associated with LTE-Advance from two perspectives: (1) a receiver that is capable of wide-frequency range of operation to cover all the LTE bands and (2) a single highly linear RF frontend to support non-contiguous-in-band CA. A novel sigma-delta-based direct-RF-to-digital receiver architecture is introduced in this work as an example of a complete integrated RF-to-digital frontend design capable to cover all the LTE bands. The design is implemented in 65 nm CMOS technology and the SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB over the 400 MHz to 4 GHz frequency range. In a different example, we propose a passive-mixer-first receiver system to provide CA support in a cost-effective and power-efficient manner. Mixer-first receiver's superb linearity performance enables the possibility of a single receiver processing the entire LTE RX band, while most of the signal conditioning can be pushed into DSP to enjoy the benefit of process scaling. This design has been demonstrated in a 28 nm bulk CMOS technology, and the overall system achieves <3 dB NF, >15 dBm IIP3 and 35 dB gain with 60 mW of power.