UC San Diego

Though the performance of many applications is dominated by memory behavior, our ability to describe, capture, compare, and recreate that behavior is quite limited. This inability underlies much of the complexity in the field of performance analysis: it is fundamentally difficult to relate benchmarks and applications or use realistic workloads to guide system design and procurement. A concise, observable, and machine-independent characterization of memory behavior is needed. This dissertation presents the Chameleon framework, an integrated solution to three classic problems in the field of memory performance analysis: reference locality modeling, accurate synthetic address trace generation, and the creation of synthetic benchmark proxies for applications. The framework includes software tools to capture a concise, machine-independent memory signature from any application and produce synthetic memory address traces that mimic that signature. It also includes the Chameleon benchmark, a fully tunable synthetic executable whose memory behavior can be dictated by these signatures. By simultaneously modeling both spatial and temporal locality, Chameleon produces uniquely accurate, general- purpose synthetic traces. Results demonstrate that the cache hit rates generated by each synthetic trace are nearly identical to those of the application it targets on dozens of memory hierarchies representing many of today's commercial offerings. This work focuses on the unique challenges of high-performance computing (HPC) where workload selection, benchmarking, system procurement, performance prediction, and application analysis present important challenges. The Chameleon framework can aid in each scenario by providing a concise representation of the memory requirements of full-scale applications that can be tractably captured and accurately mimicked