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Jitter, Phase Noise and Spurs in Frequency Multiplying Delay-locked loops: A Simple Model and Analysis
- Author(s): Yang, Dihang
- Advisor(s): Abidi, Asad Ali
- et al.
Abstract
We study the jitter performance of multiplying delay locked loops (MDLLs) and provide an effective approach to derive the phase noise of open loop MDLLs. We demonstrate that the ring oscillator phase noise models from Abidi and Hajimiri are essentially the same. Based on the analysis for MDLL jitter performance, new system models for Edge Combining DLLs and Recirculating DLLs are proposed which are accurate and simple for stability and noise analysis. Moreover, spurs caused by mismatch errors in Edge Combining DLLs are studied based on the new system model.