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Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration


This thesis presents the Simple Universal Parallel intERface (SuperCHIPS) protocol for high interconnect density heterogeneous system integration. This is enabled by fine pitch interconnects and dielet assembly at close proximity on interconnect fabric. Dramatic improvements in bandwidth, latency, and power are achieved through this integration scheme where small dielets (1-25 mm2) are attached to a Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-dielet spacing (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Simulated models indicate that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and cross-talk (<-15 dB) achieving data rates >10 Gbps per link. Further, the maximum current density for a given current is 30x lower in copper interconnects compared to conventional solder bumps. With fine interconnect pitches (<10 μm), this scheme can achieve >5-30x improvement in data bandwidth and >50x reduction in power compared to PCB-style integration. This scheme of system integration using a dielet based assembly method provides significant reduction in design and validation cost. Test vehicles were fabricated and experimental demonstration of the integration scheme is presented.

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