UC Santa Barbara

With the advent of things like autonomous vehicles, augmented reality, high-capacity wireless networks, and high performance computing, the ways in which we sense, process and transfer information are evolving, and this is driving innovation in semiconductor electronics and photonics. At the forefront of this evolution III-V semiconductors like indium phosphide (InP) and gallium arsenide (GaAs) present themselves as high performance materials both in electronics (high mobility, heterojunctions) and photonic (direct bandgap, light emission) devices. Growth of these materials is possible via metal organic chemical vapor deposition (MOCVD), an ideal tool because highly scalable and industry standard for high volume production and throughput.

In this work we explore several MOCVD selective area growth (SAG) approaches for the growth of III-V based technologies.First, we further develop a type of SAG called template assisted selective epitaxy (TASE) as a way to integrate horizontal heterojunctions (HJs) in a laterally grown structure while also allowing for planar gating. We show successful growth of horizontal HJs of InAs, GaAs and InGaAs, included in InP structures and characterized to show abrupt interfaces and crystalline material. The orientation of the templates and the substrate is chosen so that a flat vertical facet appears at the growth front allowing for the HJs to be horizontal, unlike typical planar epitaxy, enabling the design of novel electronic HJ devices like a low energy triple-HJ tunnel field effect transistor.

We then explore how III-V materials can be integrated onto CMOS compatible silicon substrates via SAG to create a low defect density pseudo substrate for the subsequent regrowth of active gain materials and the integration of photonic devices. This is attempted by leveraging aspect ratio trapping effects of TASE on Silicon or SOI (silicon on insulator) while scaling its size to a large enough area to accommodate photonic structures like micro disk lasers.Finally, we demonstrate a different SAG approach where deep (>5 micron) recesses are etched into (001) silicon. The recesses are deep enough to allow application of mature defect engineering techniques (low temperature buffers, defect filtering layers and superlattices) and obtaining an antiphase boundary (APB)-free GaAs micro ridge, while remaining underneath surface, facilitating coupling with adjacent waveguide structures.