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H.264 Codec Implementation on a Many-Core Processor Array

Abstract

Due to the rise of higher resolution video over limited transmission bandwidths, video compression algorithms have revolutionized the way we view a digital video today. H.264, also known as Advanced Video Compression (AVC), is a popular standard for the compression of video content. H.264/AVC offers excellent compression performance due to a collection of algorithmic improvements over its predecessors. The H.264/AVC standard algorithm requires a high level of computational complexity with the opportunity to compute many subtasks in parallel. Consequently, a fine-grained many-core platform is a promising solution for the H.264/AVC algorithm. In this work a baseline H.264/AVC encoder and decoder (codec) is designed and simulated on the KiloCore II chip. The encoder processes 27,239 macroblocks-per-second at 449 mW without any algorithm specific hardware. With the introduction of a motion estimation accelerator, the encoder is able to process 73,010 macroblocks-per-second at 635 mW. The decoder, on the other hand, processes 24,347 macroblocks-per-second at 482 mW. KiloCore II is a competitive platform for video compression achieving a 1.8x - 49.1x and 1.4x - 8.1x higher throughput relative to compared codec designs.

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