Department of Computer Science & Engineering

We study signal integrity effects on statistical timing analysis, e.g., interconnect and gate delay variations induced by crosstalk aggressor alignment, i.e., difference in signal arrival times in coupled neighboring interconnects. Such effects bring significant source of variation, and must be taken into account in statistical timing analysis. We establish a functional relationship between signal propagation delay and crosstalk alignment by deterministic circuit simulation, and derive closed form formulas for statistical distributions of output signal arrival times. Our proposed method can be smoothly integrated into a static timing analyzer, which runtime is dominated by sampling deterministic delay calculation, while probabilistic computation and updating take constant time. Our experimental results on 70nm technology global interconnect structures and 130nm technology industry designs show that lack of statistical crosstalk alignment consideration could lead to up to 114.65% (71.26%) differences in interconnect delay means (standard deviations), and 159.4% (147.4%) differences in gate delay means (standard deviations), while our method gives within 1.28% (3.38%) mismatch in interconnect output signal arrival time means (standard deviations), and within 2.57% (3.86%) mismatch in gate output signal arrival time means (standard deviations), respectively.

Pre-2018 CSE ID: CS2007-0883