UC San Diego

With the rapid growth of powerful digital algorithms in communications and control technology, it is now considered advantageous to partition systems such that more traditionally analog signal conditioning tasks like filtering, equalization, frequency translation are now being performed using digital circuits. In such systems, it is necessary burden the data converter to perform the conversion at higher speeds and higher resolutions to maximize the amount of information flowing in to and out of the digital domain. The analog-to-digital converter that links the "real" analog world with the computationally convenient digital domain is often a performance bottleneck in such systems. This dissertation is a study of analog techniques applied to multi-bit DACs that are required to overcome the analog limitations that makes it difficult to achieve high accuracy analog-to- digital and digital-to-analog converters. The improvement of accuracy is achieved in the analog domain using a novel technique called self-configuration. Using statistical matching properties of capacitor arrays, a pipelined ADC self-configures the MDAC capacitor array for best matching from many trial combinations of smaller capacitive sub- elements. These sub-elements having opposite error magnitudes are grouped together to form matched elements thus permitting an accurate multi-bit MDAC to be created without using an explicit trimming network. A random search algorithm enables the self-configuration process by quickly regrouping the sub-elements to reduce the spread between the reconstructed elements. The proposed state machine based permutation algorithm allows near unique permutations of the sub-elements and achieves a near unity state repetition ratio with a simple hardware implementation. An ADC system is designed with the self- configuration algorithm contained in the same die, and improvement in capacitor matching is demonstrated after the self-configuration process. A 0.18[mu]m CMOS prototype achieves 13b linearity and over 80dB SFDR at 43MS/s. The chip consumes 268mW at 1.8V and occupies 3.6mm\². A short study of an existing alternate analog calibration scheme is presented as a comparison. This scheme helps improve the matching of elements in the feedback DAC of a multi- bit delta-sigma ADC. Opportunities to improve the scheme for high-speed operation are identified and proposed solutions are verified using simulations