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High-Efficiency and High-Power CMOS Power Amplifiers for Millimeter-Wave Applications /

Abstract

This research focuses on the analysis and design of stacked-FET power amplifiers for millimeter-wave applications. We analyze the loss mechanisms in the stacked-FET PA circuit to develop the fundamental bounds on PAE and output power. Two-stack power amplifiers are designed and implemented at 45 and 90GHz achieving 19 and 15.8dbm output power with 34% and 11% PAE, respectively. The gate resistance of the stacked-FET PA is demonstrated to be a dominant source of loss at high frequency. To overcome this limitation, a multi-drive stacked-FET approach is proposed to improve the output power and efficiency. An analysis of conventional and multi-drive stacked-FET PAs demonstrates the performance improvement. A multi-drive three-stack PA is implemented in 45-nm SOI CMOS for 90GHz operation occupying 0.23 mm². This PA achieves 19dBm saturated output power at a PAE of 14% and 12dB gain at 90 GHz using a 3.4-V power supply. To achieve high output power and high efficiency with high data rates using QAM modulation, this research proposes a new stacked -FET transmitter in 45-nm SOI CMOS at 45 GHz, which shares a common DC current through an I/Q digital-to-analog converter (DAC), I/Q mixer, and stacked-FET PA to provide high voltage swing without exceeding the breakdown voltage of the transistors in the stack. The circuit approach proposed here provides high RF output power at high efficiency along with a high-resolution DAC control to transmit complex modulation schemes. The use of high- resolution DACs enables the use of digital predistortion (DPD) to improve the error vector magnitude (EVM). The proposed architecture demonstrates 21.3 dBm saturated output power at a peak PAE of 16% into a 50 Ohms load impedance at 45 GHz, generating a 1.25-Gbps QPSK at an EVM of 5.5% using digital predistortion. Considering that modern communication systems employ modulation techniques that exhibit high peak-to-average power ratios (PAPRs), demand for amplifiers with high efficiency over a wide power range is increasing. The traditional Doherty power amplifier is one of the circuits that satisfy this demand by providing peak efficiency at 6-dB back off as well as peak power. In this work, the designed stacked-FET power amplifiers are utilized to make a Doherty power amplifier and a modified Doherty PA is proposed that addresses the limitations of the traditional design. The results demonstrate 4% improved back-off PAE as well as 1.5dB higher gain in comparison to the designed traditional Doherty PAs

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