Skip to main content
Open Access Publications from the University of California

UC San Diego

UC San Diego Electronic Theses and Dissertations bannerUC San Diego

Built-In Self-Test Circuits for Silicon Phased Array Applications /


The thesis presents built-in self-test circuits for phased array applications, and the characterization of a 45 nm CMOS SOI technology for millimeter-wave systems. First, an X-Band phased-array RF integrated circuit with built-in self-test (BIST) capabilities is presented. The BIST is accomplished using a miniature capacitive coupler at the input of each channel and an on-chip I/Q vector receiver. Systematic effects introduced with BIST system are covered in detail and are calibrated out of the measurements. The BIST can be done at a rate of 1 MHz with 55 dB signal-to- noise-ratio (SNR) and allows for the measurement of an on- chip array factor. Measurements done with BIST system agree well with S-parameter data over all test conditions. Next, a 16-element phased array receiver for 76-84 GHz applications with BIST capabilities is presented. The chip contains an I/Q mixer suitable for automotive FMCW radar applications and which is also used as part of the BIST system. The chip achieves 4-bit RF amplitude and phase control, an RF to IF gain of 30-35 dB at 77-84 GHz, an I/Q balance of < 1 dB and < 10° at 76-84 GHz, and a system noise figure of 18 dB. The on-chip BIST covers the 76-84 GHz range and determines, without any calibration, the amplitude and phase of each channel, a normalized frequency response, and can measure the gain control using RF gain control. System level considerations are discussed together with extensive results showing the effectiveness of the on-chip BIST as compared to standard S-parameter measurements. For W-band transmit/receive phased-array modules, the first BIST system is presented. Low-loss high -isolation switches are attached to the RF input and output ports using quarter-wave transmission-line sections which result in a high shunt impedance when the BIST is disabled and minimal penalty in additional loss. A well- balanced W-band I/Q down-conversion mixer/receiver is also implemented on-chip and is used as an on-chip vector network analyzer. The BIST allows the measurement of the S -parameters in both transmit and receive modes with high accuracy (4-bit phase response, < 0.5 dB amplitude variation) at 90-100 GHz without any external calibration. The BIST also results in a normalized frequency response which agrees well with the measured S-parameters at 90-100 GHz. An in-depth study of a 45 nm CMOS silicon-on- insulator (SOI) technology is presented. Several transistor test cells are characterized and the effect of finger width, gate contact and gate poly pitch on transistor performance is analyzed. The measured peak ft is 264 GHz for a 30x1007 nm single-gate contact relaxed- pitch transistor and the best fmax of 283 GHz is achieved by a 58x513 nm single-gate contact regular pitch transistor. The measured transistor performance agrees well with the simulations including R/C extraction up to the top metal layer. Passive components are also characterized and their performance is predicted accurately with design kit models and electromagnetic simulations. Low noise amplifiers from Q- to W-band are developed in this technology and they achieve state-of-the -art noise figure values

Main Content
For improved accessibility of PDF content, download the file to your device.
Current View