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Open Access Publications from the University of California

Behavioral exploration with RTL library


Behavioral synthesis that takes into consideration real components as well as timing constraints is necessary for the design of today's ASIC chips. In this report, we give a methodology for design space exploration under timing constraints. To illustrate our proposed methodology, we also give several designs that implement a Square Root Algorithm. We compare these designs and give their behavioral and structural description in the Appendix.

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