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A flexible DSP block to enhance FPGA arithmetic performance

  • Author(s): Parandeh-Afshar, H
  • Cevrero, A
  • Athanasopoulos, P
  • Brisk, P
  • Leblebici, Y
  • Ienne, P
  • Editor(s): Bergmann, Neil W
  • Diessel, Oliver
  • Shannon, Lesley
  • et al.

Published Web Location

http://www1.cs.ucr.edu/faculty/philip/papers/conferences/fpt09/fpt09-fpctppg.pdf
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Abstract

We propose a new DSP block for use in modern high-performance FPGAs. Current DSP blocks contain fixed-bitwidth multipliers that can be combined efficiently to form larger multipliers. Our approach is similar, but includes a bypass layer following the partial product generator that exposes the compressor tree used for partial product reduction directly to the user. As a consequence, the proposed DSP block can accelerate multi-input addition operations in addition to multiplication. To increase the flexibility of the device, the partial product reduction tree used within our DSP block uses a fixed-function compression logic along with a field programmable compressor tree (FPCT), the latter of which is user-configurable to meet the needs of the application at hand. Multi-input addition operations can be mapped directly onto the FPCT without compromising any of the other functionality of the DSP block. © 2009 IEEE.

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