UCLA

One of the most important packaging techniques is copper electroplating. A successful electroplating, whether for back-end-of-line (BEOL) interconnects or packaging applications, depends on finding the right additives for increasing plating quality or bottom-up fill, maintaining a stable bath composition and minimizing the impurity level in the plated copper. When it comes to changes in new barrier layer, seed layer and aspect ratio, challenges arise as the process flow becomes much more complicated.In silicon interconnect fabric approach, we aim to replace traditional printed circuit board (PCB) by silicon substrate. With silicon substrate, not only can we achieve high interconnect density but also high-power applications since silicon possesses outstanding thermal properties comparing with organic substrates such as PCB. However, a dense die integration requires a high-power delivery (0.7-1W/mm2) and III generates a huge amount of heat (0.5-0.7W/mm2). The power delivery through periphery I/O is not able to supply such a great amount of power (more than 50kW on 12-inch wafer). As a result, power has to be distributed through TWVs. An excellent copper electroplating process during the fabrication is a critical process since a good quality of plating provides lower IR drops and lower heat losses. In this thesis, we develop through wafer vias (TWVs) for Si-IF to deliver the power from the back of Si- IF to the front side of the wafer which can be used for potential wafer-scaled integration or attached with power delivery/cooling system. In this work, we first demonstrate the characterization of copper electroplating process including the uniformity test and surface roughness measurement. Then we move on to the development of a reliable fabrication flow of TWVs for Si-IF that enables 3D integration packaging.