UCLA

Power consumption is a critical aspect in today's mobile environment, while higher performance remains a major design goal. In recent mobile devices, the signal processing applications are power-consuming due to the frequent use of arithmetic computations; hence they have a large impact on the overall power dissipation. Specifically, a sum-of-products is a frequently used arithmetic operation in signal processing applications. Conventional designs use separate multipliers and adders in implementing sum-of-products. In this dissertation, we focus on developing a low-power arithmetic unit to perform a sum-of-products operation. The objective of this research is to investigate the algorithmic and architectural approaches for low-power and high-performance design of a sum-of-products with multi-functional computing ability, SIMD and approximate operations, and to demonstrate its capabilities in representative signal processing applications. The key distinguishing features of our approach is to develop a sum-of-products systematically from two aspects: internal efforts considering the arithmetic architecture and external efforts considering input data characteristics. We evaluate the power, delay and area of our solutions, and then compare our designs with similar arithmetic schemes. The benchmark evaluations are used to identify benefits and limitations of our solutions in signal processing applications.