Design of a system for cm-range wireless communications
- Author(s): Gambini, Simone
- Advisor(s): Rabey, Jan M.;
- Alon, Elad
- et al.
The continuous growth in the number of mobile phone subscribers, which exceeded 3 billions by 2007 , and of the number of wireless devices and systems, led to visions of a near future in which wireless technology is so ubiquitous that 1000 Radios per person will exist. In this context, ad-hoc area networks between several consumer electronic devices located within a meter of each other will be necessary in order to reduce traffic towards the base station and reduce power consumption and interference generation. As existing air interfaces still both radiate and dissipate an order of magnitude higher power than what this future scenario requires, a new, low-power radio technology must be developed.
In this thesis, we develop a low-power transceiver with range of a few centimeters targeted to mobile-mobile data exchange. The same transceiver could also be employed in some implanted applications, as well as in distributed industrial control environments. \
The design of the air-interface for this cm-range communication system at the propagation, system and circuit levels. First, we describe an optimization methodology that enables the designer to choose, for any given antenna design, which carrier frequency results in the maximum receiver Signal-To-Noise-Ratio (SNR). We then show how by using impulse-radio signaling, the chosen high-SNR channel can be leveraged to simplify the radio receiver architecture to the simplest possible RF receiver-consisting only of an RF rectifier. To mitigate the known issues of sensitivity to interference for these rectifier-based receivers, a technique to improve selectivity that uses only baseband processing and requires no RF prefilter is introduced.
These techniques are demostrated by a transceiver test chip, implemented in a 65nm CMOS process . The transceiver dissipates 250 &mu W in receive mode, and 25 &mu W in transmit mode when operating at 1Mbps , and it integrates a timing-recovery loop that achieves jitter lower than 2nS while consuming 45 &mu W.This figures correspond to an energy per bit of 300pJ, which compares favorably with current state-of-the art.