UCLA

The research is divided into three primary sections. In the first section, a rigorous mathematical framework is developed under which net weighting methods, common in VLSI physical design, may be proven to converge, given that they satisfy several natural properties defined in the work. Several net weighting techniques from industry are analyzed within this framework and adapted so to form a class of schemes that satisfy the convergent properties. These are implemented and experimentally tested within the analytical placer mPL. In the second section, the net weighting framework is extended to statistical timing-aware placement in a novel algorithm, termed STAP, with promising experimental results. In the third section, a new approach to statistical timing-aware gate sizing, termed ProSize, is developed from current research in convex optimization.