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A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains


A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18 um CMOS full-custom design and a 0.18 um CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580 MHz operation and 10.3 mW power dissipation while performing simultaneous FIFO READ and WRITE operations at 1.8 V.

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