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Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design

  • Author(s): Cook, Chase William
  • Advisor(s): Tan, Sheldon X.-D
  • et al.
Abstract

The continued scaling of VLSI circuits has provided a wealth of opportunities and

challenges to the VLSI circuit design area. Both these challenges and opportunities, however,

require new simulation tools that can enable their solution or exploitation as classical

methods typically dealt with problem domains with smaller scales or less complexity. In

this dissertation, simulation methods are presented to address the emerging VLSI design

topics of Electromigration induced aging and Ising computing and are then applied to the

application areas of hardware security and graph partitioning respectively.

The Electromigration aging effect in VLSI circuits is a long-term reliability issue

affecting current carrying metal wires leading to IR drop degradation. Typically, simple

analytical equations can determine a wire’s effective age or if it will be affected by the EM

aging effect at all. However, these classical methods are overly conservative and can lead to

over design or unnecessary design iterations. Furthermore, it is expected that the EM aging

effect will become more severe in future Integrated Cirucits (ICs) due to increasing current

densities and the prevalance of polycrystaline copper atom structures seen at small wire

dimensions. For this reason, more comprehensive simulation techniques that can efficiently

simulate the EM effect with less conservative results can help mitigate overdesign and

increase design margins while reducing design iterations.

The area of Hardware Security is becoming increasingly important as the chip

supply chain becomes more globalized and the integrity of chips becomes more diffiuclt to

verify. Utilizing the accurate simulation techniques for EM, we can utilize this reliability

effect to demonstrate how a reliability based attack could be perpatrated. Furthermore, we

can utilize this aging effect as a defense mechanism to help us validate the integrity of an

IC and detect counterfeit chips in the component supply chain market.

Ising computing is an emerging method of solving combinatorial optimization problems

by simulating the interactions of so-called spin glasses and their interactions. Borrowing

concepts from quantum computing, this methods mimics the quantum interaction between

spin glasses in such a way that finding a ground state of these spin glass models leads

to the solution of a particular problem. In this dissertation, effective methods of simulating

the spin glass interactions using General Purpose Graphics Processing Units (GPGPUs)

and finding their ground state are developed.

In addition to the GPU based Ising model simulations, important combinatorial

problems can be mapped to the Ising model. In this dissertation the Ising solver is applied

to graph partitioning which can be utilized in VLSI design and many other domains as well.

Specifically, solvers for the maxcut problem and the balanced min-cut partitioning problem

are developed.

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