UCLA

The steady growth in global internet traffic continues to push the aggregate bandwidth requirementsin chip-to-chip communications, which is supported by an increase in both the number of lanes per chip and the per-lane data rate, rising by about a factor of two every four years. This trend dictates that both the power efficiency and area consumption of the transceivers (TRXs) be minimized so as to balance overall system costs. The problem of power consumption is further aggravated by the worsening speed-power-loss tradeoffs at high-speeds, with the state-of-the-art 56/112 Gb/s TRXs drawing between 2.5-4.5 mW/Gb/s; well above the generally-desired target of 1 mW/Gb/s. A study of these TRX architectures reveals that they employ 4-level pulse amplitude modulation (PAM4) in order to alleviate the high channel loss, but do so at the cost of reduced signal-to-noise (SNR) ratio and increased sensitivity to cross-talk and channel reflections. This dictates power hungry ‘mostly-digital’ receiver (RX) architectures which comprise of a high-speed, highly-interleaved analog-to-digital-converter (ADC) front-end and a digital back-end providing equalization and clock-and-data recovery (CDR). The high power consumption can be attributed to the high interleaving factor (40-50 channels), as well as the generation and distribution of low-jitter, multi-phase clocks to these channels. In this work, we aim to resolve these speed-power tradeoffs through novel analytical and circuit design techniques that enable a threefold reduction in both the power efficiency and area consumption. In the first part, we introduce an RX design for short to medium reach links that is based on NRZ signaling, thus avoiding an ADC-based architecture altogether, instead relying on power and area efficient ‘analog’ linear equalizer (CTLE) and decision-feedback equalizer (DFE) implementations. The issue of increased channel loss associated with NRZ modulation is resolved with design techniques that raise the loss equalization capability considerably with a minimal power penalty. Further, a new DFE-CDR co-design is introduced that ensures robust operation for high channel losses. The effectiveness of the proposed techniques is demonstrated through measurement results of a prototype RX chip fabricated in TSMC 28-nm digital CMOS technology. The RX operates at 56 Gb/s and equalizes channel losses up to 25.5 dB with a bit-error-ratio (BER) < 10-12, while consuming only 16.84 mW from a 1-V supply, and occupies a core area of only 0.018 mm2 , representing a threefold improvement in both metrics compared to the prior art. Second, we discuss the problem of clock jitter and its impact on the SNR in ADC-based topologies. We introduce a rigorous and intuitive approach that enables a simple estimation of the maximum jitter for a given SNR penalty, and show that this estimate considerably relaxes the specification set by the conventionally applied models, thus alleviating the power consumption associated with the clock generation and distribution.