An Optimization Methodology for Matrix Computation Architectures
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An Optimization Methodology for Matrix Computation Architectures

Abstract

Matrix computations such as matrix decomposition and inversion are essential for various algorithms which are employed in wireless communication. FPGAs are ideal platforms for such applications; however, the need for vast amounts of customization throughout the design process of a matrix computation core can overwhelm the designer. This paper presents an automatic generation and optimization methodology for different matrix computation architectures using a generator tool, GUSTO, that we developed to enable easy design space exploration with different parameterization options. We especially concentrate on wireless communication MIMO-OFDM applications which often use small matrix dimensions. We present automatic generation of a variety of general purpose matrix computation architectures and optimized application specific architectures. GUSTO’s application specific architectures have comparable results to published architectural implementations, but offer the advantage of providing the designer the ability to study the tradeoffs between architectures with different design parameters.

Pre-2018 CSE ID: CS2009-0936

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