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CMOS RF power amplifier design approaches for wireless communications

  • Author(s): Pornpromlikit, Sataporn
  • et al.
Abstract

This dissertation focuses on the design of CMOS power amplifiers for modern wireless handsets, where stringent linearity requirements and high power efficiency are difficult to achieve simultaneously. CMOS technology has been an attractive technology for research in fully- integrated transceivers due to its low cost and high- integration capability, as well as its continuously improving high-frequency performance. Its advantages, however, come at the cost of continuously reduced breakdown voltages, low isolation and high power loss in the substrate. To address these limitations, a stacked-FET design technique is first developed to systematically divide the voltage stress among several transistors connected in series, allowing the use of a larger supply voltage. The voltage swing of each stacked device is added in phase to provide a larger output power to the load without the requirement of a large impedance transformation. To investigate this technique, a fully- integrated 20 dBm RF power amplifier is first implemented using 0.25-[mu]m silicon-on-sapphire MOSFETs. By using triple-stacked FETs, the optimum load impedance for a 20 dBm power amplifier increases to 50 [Omega] so impedance transformation is not required at the output. Measurement of a single-stage linear power amplifier shows a small- signal gain of 17.1 dB and a saturated output power of 21.0 dBm with a power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access (CDMA) modulated signal, the power amplifier shows average output power of 16.3 dBm and PAE of 18.7% with ACPR below -42 dBc. The concept is then further demonstrated at higher voltage and power level. A single-stage quadruple- stacked-FET linear power amplifier is presented using 0.28 -[mu]m 2.5-V standard I/O FETs in a 0.13-μm silicon-on- insulator (SOI) CMOS technology. The PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a PAE of 47% at 1.9 GHz with a 6.5-V supply. Using a reverse-link IS-95 CDMA modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. The PA also shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement of an uplink wideband code division multiple access (WCDMA) modulated signal. These performances are comparable to those of GaAs -based power amplifiers. To fully exploit the advantages of higher-speed CMOS technology and the availability of co -integrated digital circuitry, a digital-intensive transceiver architecture is explored as an alternative in the second part of the dissertation. A single-ended digitally-modulated power amplifier (DPA) is demonstrated in a 0.13-[mu]m 1.2-V SOI CMOS technology, to be used in a multi-standard RF polar transmitter. The amplitude modulation is done by digitally controlling the number of activated unit amplifiers whose currents are summed at the output. The DPA is designed for multi-mode multi-band functionality by avoiding frequency-selective components, except for the final-stage output matching network. The measured DPA delivers a 24.9-dBm peak output power at 900 MHz with a maximum power efficiency of 62.7%. Similar high -efficiency performance is also exhibited at 1.92 GHz with a reconfigured matching network. By employing a digital pre-distortion technique, the DPA could meet linearity requirements for both the enhanced data rate for GSM evolution (EDGE) and WCDMA standards

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