UC Santa Barbara

While the compute part keeping scaling for decades, it becomes more and more difficult for the memory part to catch up. This mismatch raises two grand challenges. One is referred to as the "Memory Wall", in which case the memory latency and bandwidth turn to be the bottleneck, slowing down the system no matter how computing resource improves. The other one is referred to as the ``Power Wall'', which demands high power efficiency due to a limited power budget, whereas the energy spent on the memory accesses dominates the total energy consumption.

To address those challenges, this dissertation focuses on designing memory-centric architectures to bridge the gap between compute and memory. Two types of memory-centric architecture have been investigated. The first one is the compute-capable memory architecture, which moves computing resources to the memory side. The in-memory computing scheme explores larger bandwidth and reduces data movement overhead. The second one is the memory-rich accelerator architecture, which is designed with tightly coupled high performance computing resource and large-capacity on-die memory. The in-situ computing design provides benefits as a non Von Neumann architecture. This dissertation has proposed five architectures, which cover both compute-capable memory and memory-rich accelerator architectures, both the offshore DRAM and emerging non-volatile memory technologies, and a large range of the important applications, such as deep learning, database, graph processing.