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A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

  • Author(s): Bartoldus, R;
  • Claus, R;
  • Garelli, N;
  • Herbst, RT;
  • Huffer, M;
  • Iakovidis, G;
  • Iordanidou, K;
  • Kwan, K;
  • Kocian, M;
  • Lankford, AJ;
  • Moschovakos, P;
  • Nelson, A;
  • Ntekas, K;
  • Ruckman, L;
  • Russell, J;
  • Schernau, M;
  • Schlenker, S;
  • Su, D;
  • Valderanis, C;
  • Wittgen, M;
  • Yildiz, SC
  • et al.

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

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