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Physics Department

UC Santa Cruz

An Investigation of Depletion in AstroPix, a High Voltage Monolithic CMOS Sensor

The data associated with this publication are available upon request.
Abstract

Future space based particle physics experiments require detectors to be low power to ensure efficiency where no large amounts of energy can be continuously provided. The AstroPix chip aims for a power consumption of 1.5mW/cm2 and energy resolution of 2% at600keV per sensor. To determine the readiness of several wafers of different resistivities, 3 experiments were conducted. CV and IV data were taken using a probe station in SCIPP’s electronics room. The results determined that while the IV relationship looked normal for sensors with lower resistivities (from wafers 2 and 6), the sensors with higher resistivities (from wafers 10 and 11) had much higher current than anticipated, which inhibited the use of high voltage as breakdown occurred early.

Another experiment consisted of taking data from a laser edge-TCT scan; this test confirmed the strange behavior of high resistivity chips as voltage amplitude pulses losttheir shape and amplitude with higher bias voltages which is contrary to intuition and the behavior of the lower resistivity chips. This led to the idea that with a high enough bias voltage, the leakage current incapacitates some of the transistors in W10 and W11 chips.

The last experiment conducted was an infrared radiation scan of certain chips with the intention of furthering the investigation of the aforementioned anomalies. The result was that the backs of the high resistivity chips had different potentials than the fronts of the chips; when conducting tape was used on the backside of these chips, the current hit compliance (10mA) at a low voltage (10V). However, when using insulating tape or testing the chip on a metal chuck with probes in the high voltage and grounding pads, the chip was able to reach a higher voltage (220V) with the same current limit. This test shed lighton instances of higher power dissipation along the edges of certain chips which led to ideas about design flaws and differences in how different chips distributed current and dissipated power.

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